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1 LT3027 sn3027 3027fs v out 100 v/div 20 v rms 3027 ta01b applicatio s u descriptio u features typical applicatio u dual 100ma, low dropout, low noise, micropower regulator with independent inputs low noise: 20 v rms (10hz to 100khz) low quiescent current: 25 a/channel independent inputs wide input voltage range: 1.8v to 20v output current: 100ma/channel very low shutdown current: <0.1 a low dropout voltage: 300mv at 100ma adjustable output from 1.22v to 20v stable with 1 f output capacitor stable with aluminum, tantalum or ceramic capacitors reverse battery protected no protection diodes needed overcurrent and overtemperature protected tracking/sequencing capability thermally enhanced 10-lead msop and dfn packages the lt 3027 is a dual, micropower, low noise, low drop- out regulator with independent inputs. with an external 0.01 f bypass capacitor, output noise is a low 20 v rms over a 10hz to 100khz bandwidth. designed for use in battery-powered systems, the low 25 a quiescent current per channel makes it an ideal choice. in shutdown, quies- cent current drops to less than 0.1 a. shutdown control is independent for each channel, allowing for flexibility in power management. the device is capable of operating over an input voltage from 1.8v to 20v, and can supply 100ma of output current from each channel with a drop- out voltage of 300mv. quiescent current is well controlled in dropout. the LT3027 regulator is stable with output capacitors as low as 1 f. small ceramic capacitors can be used without the series resistance required by other regulators. internal protection circuitry includes reverse battery pro- tection, current limiting and thermal limiting protection. the device is available as an adjustable device with a 1.22v reference voltage. the LT3027 regulator is available in the thermally enhanced 10-lead msop and low profile (0.75mm) 3mm 3mm dfn packages. 10hz to 100khz output noise 3.3v/2.5v low noise regulators cellular phones pagers battery-powered systems frequency synthesizers wireless modems tracking/sequencing power supplies , ltc and lt are registered trademarks of linear technology corporation. in1 0.01 f 0.01 f 10 f 3027 ta01 out1 v in1 3.7v to 20v byp1 adj1 out2 byp2 adj2 gnd LT3027 3.3v at 100ma 20 v rms noise 2.5v at 100ma 20 v rms noise 1 f shdn1 in2 v in2 2.9v to 20v 1 f shdn2 10 f 422k 249k 261k 249k protected by u.s. patents, including 6118263, 6144250.
2 LT3027 sn3027 3027fs (note 1) in1, in2 pin voltage .............................................. 20v out1, out2 pin voltage ....................................... 20v input to output differential voltage ....................... 20v adj1, adj2 pin voltage ......................................... 7v byp1, byp2 pin voltage ....................................... 0.6v shdn1, shdn2 pin voltage ................................. 20v output short-circut duration .......................... indefinite parameter conditions min typ max units minimum input voltage i load = 100ma 1.8 2.3 v (notes 3, 10) adj1, adj2 pin voltage v in = 2v, i load = 1ma 1.205 1.220 1.235 v (note 3, 4) 2.3v < v in < 20v, 1ma < i load < 100ma 1.190 1.220 1.250 v line regulation (note 3) ? v in = 2v to 20v, i load = 1ma 110 mv load regulation (note 3) v in = 2.3v, ? i load = 1ma to 100ma 1 12 mv v in = 2.3v, ? i load = 1ma to 100ma 25 mv dropout voltage i load = 1ma 0.10 0.15 v v in = v out(nominal) i load = 1ma 0.19 v (notes 5, 6, 10) i load = 10ma 0.17 0.22 v i load = 10ma 0.29 v i load = 50ma 0.24 0.28 v i load = 50ma 0.38 v i load = 100ma 0.30 0.35 v i load = 100ma 0.45 v the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 2) consult factory for parts specified with wider operating temperature ranges. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics LT3027edd LT3027idd order part number dd part marking operating junction temperature range (note 2) ............................................ 40 c to 125 c storage temperature range dd package ...................................... 65 c to 125 c mse package ................................... 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c top view dd package 10-lead (3mm 3mm) plastic dfn exposed pad (pin 11) is gnd must be soldered to pcb 10 9 6 7 8 4 5 3 2 1 out2 in2 in1 shdn1 out1 byp2 adj2 shdn2 adj1 byp1 11 1 2 3 4 5 byp2 adj2 shdn2 adj1 byp1 10 9 8 7 6 out2 in2 in1 shdn1 out1 top view mse package 10-lead plastic msop exposed pad (pin 11) is gnd must be soldered to pcb 11 LT3027emse LT3027imse order part number mse part marking t jmax = 125 c, ja = 43 c/ w, jc = 3 c/ w t jmax = 150 c, ja = 40 c/ w, jc = 10 c/ w lbkn lbmc ltbkk ltbmd
3 LT3027 sn3027 3027fs parameter conditions min typ max units gnd pin current (per channel) i load = 0ma 25 50 a v in = v out(nominal) i load = 1ma 60 120 a (notes 5, 7) i load = 10ma 250 400 a i load = 50ma 12 ma i load = 100ma 2.4 4 ma output voltage noise c out = 10 f, c byp = 0.01 f, i load = 100ma, bw = 10hz to 100khz 20 v rms adj1/adj2 pin bias current (notes 3, 8) 30 100 na shutdown threshold v out = off to on 0.8 1.4 v v out = on to off 0.25 0.65 v shdn1/shdn2 pin current v shdn = 0v 0 0.5 a (note 9) v shdn = 20v 13 a quiescent current in shutdown v in = 6v, v shdn = 0v (both shdn pins) 0.01 0.1 a ripple rejection (note 3) v in = 2.72v (avg), v ripple = 0.5v p-p , f ripple = 120hz, 55 65 db i load = 100ma current limit v in = 7v, v out = 0v 200 ma v in = 2.3v, ? v out = 5% 110 ma input reverse leakage current v in = 20v, v out = 0v 1ma the denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. (note 2) electrical characteristics note 5: to satisfy requirements for minimum input voltage, the LT3027 is tested and specified for these conditions with an external resistor divider (two 250k resistors) for an output voltage of 2.44v. the external resistor divider will add a 5 a dc load on the output. note 6: dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output current. in dropout, the output voltage will be equal to: v in ?v dropout . note 7: gnd pin current is tested with v in = 2.44v and a current source load. this means the device is tested while operating in its dropout region or at the minimum input voltage specification. this is the worst-case gnd pin current. the gnd pin current will decrease slightly at higher input voltages. note 8: adj1 and adj2 pin bias current flows into the pin. note 9: shdn1 and shdn2 pin current flows into the pin. note 10: for the LT3027 dropout voltage will be limited by the minimum input voltage specification under some output voltage/load conditions. see the curve of minimum input voltage in the typical performance characteristics. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: the LT3027 regulator is tested and specified under pulse load conditions such that t j t a . the LT3027e is guaranteed to meet performance specifications from 0 c to 125 c junction temperature. specifications over the 40 c to 125 c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3027i is guaranteed and tested over the full 40 c to 125 c operating junction temperature range. note 3: the LT3027 is tested and specified for these conditions with the adj1/adj2 pin connected to the corresponding out1/out2 pin. note 4: operating conditions are limited by maximum junction temperature. the regulated output voltage specification will not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, the output current range must be limited. when operating at maximum output current, the input voltage range must be limited.
4 LT3027 sn3027 3027fs output current (ma) 500 450 400 350 300 250 200 150 100 50 0 dropout voltage (mv) 3027 g02 0 102030 40 50 60 70 80 90 100 t j 125 c t j 25 c = test points temperature ( c) ?0 quiescent current ( a) 100 3027 g03 050 40 35 30 25 20 15 10 5 0 25 25 75 125 v in = 6v r l = 250k i l = 5 a v shdn = v in v shdn = 0v guaranteed dropout voltage quiescent current dropout voltage temperature ( c) ?0 dropout voltage (mv) 0 50 75 3027 g03 ?5 25 100 125 i l = 100ma i l = 50ma i l = 10ma i l = 1ma 500 450 400 350 300 250 200 150 100 50 0 output current (ma) 500 450 400 350 300 250 200 150 100 50 0 dropout voltage (mv) 3027 g01 0 102030 40 50 60 70 80 90 100 t j = 125 c t j = 25 c typical dropout voltage typical perfor a ce characteristics uw input voltage (v) 02 6 10 14 18 quiescent current ( a) 30 25 20 15 10 5 0 4 8 12 16 3027 g06 20 t j = 25 c r l = 250k i l = 5 a v shdn = v in v shdn = 0v quiescent current adj1 or adj2 pin voltage temperature ( c) ?0 adj pin voltage (v) 100 3027 g05 050 1.240 1.235 1.230 1.225 1.220 1.215 1.210 1.205 1.200 25 25 75 125 i l = 1ma input voltage (v) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 gnd pin current (ma) 3027 g07 0123 4 5 67 8910 t j = 25 c *for v out = 1.22v r l = 12.2 ? i l = 100ma* r l = 24.4 ? i l = 50ma* r l = 122 ? i l = 10ma* r l = 1.22k i l = 1ma* output current (ma) 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 gnd pin current (ma) 3027 g08 0 102030 40 50 60 70 80 90 100 v in = v out(nominal) + 1v gnd pin current gnd pin current vs i load temperature ( c) ?0 shdn pin threshold (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 75 3027 g09 ?5 25 100 125 i l = 1ma shdn1 or shdn2 pin threshold (on-to-off)
5 LT3027 sn3027 3027fs typical perfor a ce characteristics uw shdn1 or shdn2 pin input current adj1 or adj2 pin bias current current limit temperature ( c) ?0 shdn pin input current ( a) 0 50 75 3027 g12 ?5 25 100 125 v shdn = 20v 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 temperature ( c) ?0 adj pin bias current (na) 100 90 80 70 60 50 40 30 20 10 0 0 50 75 3027 g13 ?5 25 100 125 input voltage (v) 0 short-circuit current (ma) 2 4 5 3027 g14 1 3 6 7 350 300 250 200 150 100 50 0 v out = 0v t j = 25 c current limit temperature ( c) ?0 current limit (ma) 0 50 75 3027 g15 ?5 25 100 125 350 300 250 200 150 100 50 0 v in = 7v v out = 0v shdn pin voltage (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 shdn pin input current ( a) 3027 g11 0123 4 5 67 8910 shdn1 or shdn2 pin input current temperature ( c) ?0 shdn pin threshold (v) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 50 75 3027 g10 ?5 25 100 125 i l = 100ma i l = 1ma shdn1 or shdn2 pin threshold (off-to-on) input ripple rejection frequency (khz) ripple rejection (db) 80 70 60 50 40 30 20 10 0 0.01 1 10 1000 3027 g18 0.1 100 i l = 100ma v in = 2.3v + 50mv rms ripple c byp = 0 c out = 10 f c out = 1 f input ripple rejection frequency (khz) ripple rejection (db) 80 70 60 50 40 30 20 10 0 0.01 1 10 1000 3027 g19 0.1 100 i l = 100ma v in = 2.3v + 50mv rms ripple c out = 10 f c byp = 0.01 f c byp = 1000pf c byp = 100pf
6 LT3027 sn3027 3027fs typical perfor a ce characteristics uw temperature ( c) ?0 ripple rejection (db) 100 3027 g20 050 80 70 60 50 40 30 20 10 0 25 25 75 125 v in = v out (nominal) + 1v + 0.5v p-p ripple at f = 120hz i l = 50ma input ripple rejection minimum input voltage temperature ( c) ?0 minimum input voltage (v) 2.5 2.0 1.5 1.0 0.5 0 0 50 75 3027 g22 ?5 25 100 125 i l = 100ma i l = 50ma load regulation output noise spectral density output noise spectral density rms output noise vs bypass capacitor 50 s/div c out1 , c out2 = 10 f c byp1 , c byp2 = 0.01 f ? i l1 = 10ma to 100ma ? i l2 = 10ma to 100ma v in = 6v, v out1 = v out2 = 5v v out1 20mv/div v out2 20mv/div 3027 g21a frequency (khz) channel-to-channel isolation (db) 100 90 80 70 60 50 40 30 20 10 0 0.01 1 10 1000 3027 g21b 0.1 100 i load = 100ma per channel temperature ( c) ?0 load regulation (mv) 0 ? ? ? ? ? ? ? ? ? ?0 05075 3027 g23 ?5 25 100 125 ? il = 1ma to 100ma frequency (khz) output noise spectral density ( v/ hz) 0.01 1 10 100 3027 g24 0.1 10 1 0.1 0.01 v out set for 5v v out =v adj c out = 10 f c byp = 0 i l = 100ma frequency (khz) output noise spectral density ( v/ hz) 0.01 1 10 100 3027 g25 0.1 10 1 0.1 0.01 v out set for 5v v out =v adj c out = 10 f i l = 100ma c byp = 1000pf c byp = 100pf c byp = 0.01 f c byp (pf) 10 output noise ( v rms ) 160 140 120 100 80 60 40 20 0 100 1k 10k 3027 g26 v out set for 5v v out =v adj c out = 10 f i l = 100ma f = 10hz to 100khz channel-to-channel isolation channel-to-channel isolation
7 LT3027 sn3027 3027fs transient response c byp = 0 transient response c byp = 0.01 f typical perfor a ce characteristics uw 10hz to 100khz output noise c byp = 0 v out 100 v/div 10hz to 100khz output noise c byp = 100pf 1ms/div c out = 10 f i l = 100ma v out set for 5v out v out 100 v/div 1ms/div c out = 10 f i l = 100ma v out set for 5v out rms output noise vs load current (10hz to 100khz) 10hz to 100khz output noise c byp = 1000pf v out 100 v/div 10hz to 100khz output noise c byp = 0.01 f 1ms/div c out = 10 f i l = 100ma v out set for 5v out v out 100 v/div 1ms/div c out = 10 f i l = 100ma v out set for 5v out time ( s) 0.2 0.1 0 0.1 0.2 output voltage deviation (v) 100 50 0 load current (ma) 3027 g32 0 400 800 1200 1600 2000 v in = 6v c in = 10 f c out = 10 f v out set for 5v out time ( s) 0.04 0.02 0 0.02 0.04 output voltage deviation (v) 100 50 0 load current (ma) 3027 g33 0 40 60 100 20 80 120 140 180 160 200 v in = 6v c in = 10 f c out = 10 f v out set for 5v out load current (ma) 0.01 output noise ( v rms ) 160 140 120 100 80 60 40 20 0 0.1 1 100 10 3027 g27 v out set for 5v v out set for 5v v out =v adj v out =v adj c out = 10 f c byp = 0 f c byp = 0.01 f 3027 g30 3027 g31 3027 g28 3027 g29
8 LT3027 sn3027 3027fs shdn1/shdn2 (pins 7/3): shutdown. the shdn1/shdn2 pins are used to put the corresponding channel of the LT3027 regulator into a low power shutdown state. the output will be off when the pin is pulled low. the shdn1/shdn2 pins can be driven either by 5v logic or open-collector logic with pull-up resistors. the pull-up resistors are required to supply the pull-up current of the open-collector gates, normally several microamperes, and the shdn1/shdn2 pin current, typically 1 a. if unused, the pin must be connected to v in . the device will not function if the shdn1/shdn2 pins are not connected. in1/in2 (pins 8/9): inputs. power is supplied to the device through the in pins. a bypass capacitor is required on this pin if the device is more than six inches away from the main input filter capacitor. in general, the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-powered circuits. a bypass capacitor in the range of 1 f to 10 f is sufficient. the LT3027 regulator is designed to withstand reverse volt- ages on the in pin with respect to ground and the out pin. in the case of a reverse input, which can happen if a battery is plugged in backwards, the device will act as if there is a diode in series with its input. there will be no reverse current flow into the regulator and no reverse voltage will appear at the load. the device will protect both itself and the load. exposed pad (pin 11): ground. this pin must be soldered to the pcb and electrically connected to ground. adj1/adj2 (pins 4/2): adjust pin. these are the inputs to the error amplifiers. these pins are internally clamped to 7v. they have a bias current of 30na which flows into the pin (see curve of adj1/adj2 pin bias current vs tempera- ture in the typical performance characteristics section). the adj1 and adj2 pin voltage is 1.22v referenced to ground and the output voltage range is 1.22v to 20v. byp1/byp2 (pins 5/1): bypass. the byp1/byp2 pins are used to bypass the reference of the LT3027 regulator to achieve low noise performance from the regulator. the byp1/byp2 pins are clamped internally to 0.6v (one v be ) from ground. a small capacitor from the correspond- ing output to this pin will bypass the reference to lower the output voltage noise. a maximum value of 0.01 f can be used for reducing output voltage noise to a typical 20 v rms over a 10hz to 100khz bandwidth. if not used, this pin must be left unconnected. out1/out2 (pins 6/10): output. the outputs supply power to the loads. a minimum output capacitor of 1 f is required to prevent oscillations. larger output capacitors will be required for applications with large transient loads to limit peak voltage transients. see the applications information section for more information on output ca- pacitance and reverse output characteristics. uu u pi fu ctio s
9 LT3027 sn3027 3027fs applicatio s i for atio wu uu the LT3027 is a dual 100ma low dropout regulator with independent inputs, micropower quiescent current and shutdown. the device is capable of supplying 100ma per channel at a dropout voltage of 300mv. output voltage noise can be lowered to 20 v rms over a 10hz to 100khz bandwidth with the addition of a 0.01 f reference bypass capacitor. additionally, the reference bypass capacitor will improve transient response of the regulator, lowering the settling time for transient load conditions. the low oper- ating quiescent current (25 a per channel) drops to less than 1 a in shutdown. in addition to the low quiescent current, the LT3027 regulator incorporates several pro- tection features which make it ideal for use in battery- powered systems. the device is protected against reverse input voltages. additionally, in dual supply applications where the regulator load is returned to a negative supply, the output can be pulled below ground by as much as 20v and still allow the device to start and operate. adjustable operation the LT3027 has an output voltage range of 1.22v to 20v. the output voltage is set by the ratio of two external resis- tors as shown in figure 1. the device servos the output to maintain the corresponding adj pin voltage at 1.22v ref- erenced to ground. the current in r1 is then equal to 1.22v/ r1 and the current in r2 is the current in r1 plus the adj pin bias current. the adj pin bias current, 30na at 25 c, flows through r2 into the adj pin. the output voltage can be calculated using the formula in figure 1. the value of r1 should be no greater than 250k to minimize errors in the output voltage caused by the adj pin bias current. note that in shutdown the output is turned off and the divider current will be zero. curves of adj pin voltage vs temperature and adj pin bias current vs temperature appear in the typical performance characteristics. the device is tested and specified with the adj pin tied to the corresponding out pin for an output voltage of 1.22v. specifications for output voltages greater than 1.22v will be proportional to the ratio of the desired output voltage to 1.22v: v out /1.22v. for example, load regulation for an output current change of 1ma to 100ma is 1mv typical at v out = 1.22v. at v out = 12v, load regulation is: (12v/1.22v)(?mv) = 9.8mv bypass capacitance and low noise performance the LT3027 regulator may be used with the addition of a bypass capacitor from v out to the corresponding byp pin to lower output voltage noise. a good quality low leakage capacitor is recommended. this capacitor will bypass the reference of the regulator, providing a low frequency noise pole. the noise pole provided by this bypass capacitor will lower the output voltage noise to as low as 20 v rms with the addition of a 0.01 f bypass capacitor. using a bypass capacitor has the added benefit of improving transient response. with no bypass capacitor and a 10 f output capacitor, a 10ma to 100ma load step will settle to within 1% of its final value in less than 100 s. with the addition of a 0.01 f bypass capacitor, the output will stay within 1% for a 10ma to 100ma load step (see transient reponse in typical performance characteristics section). however, regulator start-up time is inversely proportional to the size of the bypass capacitor, slowing to 15ms with a 0.01 f bypass capacitor and 10 f output capacitor. figure 1. adjustable operation in 3027 f01 r2 LT3027 out v in v out adj gnd r1 + vv r r ir vv inaatc output range v to v out adj adj adj =+ ? ? ? ? ? ? + ()() = = 122 1 2 1 2 122 30 25 122 20 . . = .
10 LT3027 sn3027 3027fs applicatio s i for atio wu uu output capacitance and transient response the LT3027 regulator is designed to be stable with a wide range of output capacitors. the esr of the output capaci- tor affects stability, most notably with small capacitors. a minimum output capacitor of 1 f with an esr of 3 ? or less is recommended to prevent oscilla- tions. the LT3027 is a micropower device and output transient response will be a function of output capaci- tance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. bypass capacitors, used to decouple individual components powered by the LT3027, will increase the effective output capacitor value. with larger capacitors used to bypass the reference (for low noise operation), larger values of output capacitors are needed. for 100pf of bypass capacitance, 2.2 f of output capacitor is recommended. with a 330pf bypass capacitor or larger, a 3.3 f output capacitor is recom- mended. the shaded region of figure 2 defines the region over which the LT3027 regulator is stable. the minimum esr needed is defined by the amount of bypass capaci- tance used, while the maximum esr is 3 ? . extra consideration must be given to the use of ceramic capacitors. ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics used are z5u, y5v, x5r and x7r. the z5u and y5v dielectrics are good for providing high capacitances in a small package, but exhibit strong voltage and tem- perature coefficients as shown in figures 3 and 4. when used with a 5v regulator, a 10 f y5v capacitor can exhibit an effective value as low as 1 f to 2 f over the operating temperature range. the x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. figure 2. stability output capacitance ( f) 1 esr ( ? ) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 310 3027 f02 245 6 78 9 stable region c byp = 330pf c byp = 100pf c byp = 0 c byp > 3300pf figure 4. ceramic capacitor temperature characteristics figure 3. ceramic capacitor dc bias characteristics temperature ( c) ?0 40 20 0 ?0 ?0 ?0 ?0 100 25 75 3027 f04 ?5 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10 f dc bias voltage (v) change in value (%) 3027 f03 20 0 ?0 ?0 ?0 ?0 100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10 f
11 LT3027 sn3027 3027fs for continuous normal conditions, the maximum junction temperature rating of 125 c must not be exceeded. it is important to give careful consideration to all sources of thermal resistance from junction to ambient. additional heat sources mounted nearby must also be considered. for surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the pc board and its copper traces. copper board stiffeners and plated through-holes can also be used to spread the heat gener- ated by power devices. the following tables list thermal resistance for several different board sizes and copper areas. all measurements were taken in still air on 3/32" fr-4 board with one ounce copper. table 1. mse package, 10-lead msop copper area thermal resistance topside* backside board area (junction-to-ambient) 2500mm 2 2500mm 2 2500mm 2 40 c/w 1000mm 2 2500mm 2 2500mm 2 45 c/w 225mm 2 2500mm 2 2500mm 2 50 c/w 100mm 2 2500mm 2 2500mm 2 62 c/w *device is mounted on topside. table 2. dd package, 10-lead dfn copper area thermal resistance topside* backside board area (junction-to-ambient) 2500mm 2 2500mm 2 2500mm 2 40 c/w 1000mm 2 2500mm 2 2500mm 2 45 c/w 225mm 2 2500mm 2 2500mm 2 50 c/w 100mm 2 2500mm 2 2500mm 2 62 c/w *device is mounted on topside. the thermal resistance juncton-to-case ( jc ), measured at the exposed pad on the back of the die is 10 c/w. calculating junction temperature example: given an output voltage on the first channel of 3.3v, an output voltage of 2.5v on the second channel, an input voltage range of 4v to 6v, output current ranges of 0ma to 100ma for the first channel and 0ma to 50ma for the second channel, with a maximum ambient tempera- ture of 50 c, what will the maximum junction temperature be? voltage and temperature coefficients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. for a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. a ceramic capaci- tor produced figure 5? trace in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. applicatio s i for atio wu uu thermal considerations the power handling capability of the device will be limited by the maximum rated junction temperature (125 c). the power dissipated by the device will be made up of two components (for each channel): 1. output current multiplied by the input/output voltage differential: (i out )(v in ?v out ), and 2. gnd pin current multiplied by the input voltage: (i gnd )(v in ). the ground pin current can be found by examining the gnd pin current curves in the typical performance characteristics section. power dissipation will be equal to the sum of the two components listed above. power dissipation from both channels must be considered dur- ing thermal analysis. the LT3027 regulator has internal thermal limiting de- signed to protect the device during overload conditions. 100ms/div 3027 f05 v out 500 v/div figure 5. noise resulting from tapping on a ceramic capacitor c out = 10 f c byp = 0.01 f i load = 100ma
12 LT3027 sn3027 3027fs the power dissipated by each channel of the device will be equal to: i out(max) (v in(max) ?v out ) + i gnd (v in(max) ) where (for the first channel): i out(max) = 100ma v in(max) = 6v i gnd at (i out = 100ma, v in = 6v) = 2ma so: p1 = 100ma(6v ?3.3v) + 2ma(6v) = 0.28w and (for the second channel): i out(max) = 50ma v in(max) = 6v i gnd at (i out = 50ma, v in = 6v) = 1ma so: p2 = 50ma(6v ?2.5v) + 1ma(6v) = 0.18w the thermal resistance will be in the range of 40 c/w to 60 c/w depending on the copper area. so the junction temperature rise above ambient will be approximately equal to: (0.28w + 018w)(60 c/w) = 27.8 c the maximum junction temperature will then be equal to the maximum junction temperature rise above ambient plus the maximum ambient temperature or: t jmax = 50 c + 27.8 c = 77.8 c protection features the LT3027 regulator incorporates several protection fea- tures which makes it ideal for use in battery-powered cir- cuits. in addition to the normal protection features asso- ciated with monolithic regulators, such as current limiting and thermal limiting, the devices are protected against reverse input voltages and reverse voltages from output to input. current limit protection and thermal overload protection are intended to protect the device against current overload conditions at the output of the device. for normal opera- tion, the junction temperature should not exceed 125 c. the input of the device will withstand reverse voltages of applicatio n s i n for m atio n wu u u 20v. current flow into the device will be limited to less than 1ma (typically less than 100 a) and no negative voltage will appear at the output. the device will protect both itself and the load. this provides protection against batteries which can be plugged in backward. the output of the LT3027 can be pulled below ground without damaging the device. if the input is left open circuit or grounded, the output can be pulled below ground by 20v. the output will act like an open circuit; no current will flow out of the pin. if the input is powered by a voltage source, the output will source the short-circuit current of the de- vice and will protect itself by thermal limiting. in this case, grounding the shdn pins will turn off the device and stop the output from sourcing the short-circuit current. the adj pins can be pulled above or below ground by as much as 7v without damaging the device. if the input is left open circuit or grounded, the adj pins will act like an open circuit when pulled below ground and like a large resistor (typically 100k) in series with a diode when pulled above ground. in situations where the adj pins are connected to a resis- tor divider that would pull the pins above their 7v clamp voltage if the output is pulled high, the adj pin input cur- rent must be limited to less than 5ma. for example, a re- sistor divider is used to provide a regulated 1.5v output from the 1.22v reference when the output is forced to 20v. the top resistor of the resistor divider must be chosen to limit the current into the adj pin to less than 5ma when the adj pin is at 7v. the 13v difference between output and adj pin divided by the 5ma maximum current into the adj pin yields a minimum top resistor value of 2.6k. in circuits where a backup battery is required, several dif- ferent input/output conditions can occur. the output volt- age may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open circuit. when the in pins of the LT3027 are forced below the cor- responding out pins or the out pins are pulled above the in pins, input current will typically drop to less than 2 a. this can happen if the input of the device is connected to a discharged (low voltage) battery and the output is held up by either a backup battery or a second regulator circuit. the state of the shdn pins will have no effect on the reverse output current when the output is pulled above the input.
13 LT3027 sn3027 3027fs typical applicatio s u out1 byp1 adj1 out2 byp2 adj2 in1 shdn1 shdn2 LT3027 1 f v in1 3.7v to 20v in2 1 f v in2 2.9v to 20v off on 0.01 f 0.01 f 422k 261k 249k 249k 10 f 10 f 3027 ta02a 3.3v at 100ma 2.5v at 100ma gnd v shdn1/shdn2 1v/div v out1 1v/div v out2 1v/div 2ms/div 3027 ta02b c byp (pf) 10 0.1 startup time (ms) 1 10 100 100 1000 10000 3027 ta02c noise bypassing slows startup, allows outputs to track startup time power supply controller provides coincident tracking out1 byp1 out2 byp2 LT3027 10 f 1 f 10 f 243k 3027 ta04 2.5v 3.3v v in 3.3v 1.8v gnd in1 in2 115k shdn1 adj1 adj2 shdn2 115k 93.1k 121k 255k 243k 255k fb1 status sdo fb2 ltc2923 gnd v ol gate ramp rampbuf track2 154k 100k on track1 10nf q1
14 LT3027 sn3027 3027fs 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dd10) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc u package descriptio dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699)
15 LT3027 sn3027 3027fs msop (mse) 0603 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ?.011) typ 0.127 0.076 (.005 .003) 0.86 (.034) ref 0.50 (.0197) bsc 12 3 45 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8 9 10 10 1 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ?6 typ detail ? detail ? gauge plane 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 2.083 0.102 (.082 .004) 2.794 0.102 (.110 .004) 0.50 (.0197) bsc bottom view of exposed pad option 1.83 0.102 (.072 .004) 2.06 0.102 (.081 .004) u package descriptio mse package 10-lead plastic msop (reference ltc dwg # 05-08-1663) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 LT3027 sn3027 3027fs lt/tp 0804 1k ?printed in usa ? linear technology corporation 2004 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com typical applicatio s u out1 byp1 adj1 out2 byp2 adj2 LT3027 1 f v in1 3.7v to 20v off on 0.01 f 0.01 f 422k 261k 249k 249k 35.7k 28k 10 f 10 f 3027 ta03a 3.3v at 100ma 2.5v at 100ma gnd 0.47 f in1 1 f v in2 2.9v to 20v in2 shdn1 shdn2 v shdn1 1v/div v out1 1v/div v out2 1v/div 2ms/div 3027 ta03b v shdn1 1v/div v out1 1v/div v out2 1v/div 2ms/div 3027 ta03c startup sequencing turn-on waveforms turn-off waveforms part number description comments lt1185 3a, negative ldo accurate programmable current limit, remote sense v in : 35v to 4.2v, v out(min) = 2.40v, dropout voltage = 0.8v, i q = 2.5ma, i sd = <1 a, v out = adj., to220-5 package lt1761 100ma, low noise micropower, ldo low noise < 20 v rms , stable with 1 f ceramic capacitors, v in : 1.8v to 20v, v out(min) = 1.22v, dropout voltage = 0.3v, i q = 20 a, i sd = <1 a, v out = adj., 1.5, 1.8, 2, 2.5, 2.8, 3, 3.3, 5, thinsot package lt1762 150ma, low noise micropower, ldo low noise < 20 v rms , v in : 1.8v to 20v, v out(min) = 1.22v, dropout voltage = 0.3v, i q = 25 a, i sd = <1 a, v out = adj., 2.5, 3, 3.3, 5, ms8 package lt1763 500ma, low noise micropower, ldo low noise < 20 v rms , v in : 1.8v to 20v, v out(min) = 1.22v, dropout voltage = 0.3v, i q = 30 a, i sd = <1 a, v out = 1.5, 1.8, 2.5, 3, 3.3, 5, s8 package lt1764/lt1764a 3a, low noise, fast transient response, ldo low noise < 40 v rms , "a" version stable with ceramic capacitors, v in : 2.7v to 20v, v out(min) = 1.21v, dropout voltage = 0.34v, i q = 1ma, i sd = <1 a, v out = 1.8, 2.5, 3.3, dd, to220 packages ltc1844 150ma, very low drop-out ldo low noise < 30 v rms , stable with 1 f ceramic capacitors, v in : 1.6v to 6.5v, v out(min) = 1.25v, dropout voltage = 0.08v, i q = 40 a, i sd = <1 a, v out = adj., 1.5, 1.8, 2.5, 2.8, 3.3, thinsot package lt1962 300ma, low noise micropower, ldo low noise < 20 v rms , v in : 1.8v to 20v, v out(min) = 1.22v, dropout voltage = 0.27v, i q = 30 a, i sd = <1 a, v out = 1.5, 1.8, 2.5, 3, 3.3, 5, ms8 package lt1963/lt1963a 1.5a, low noise, fast transient response, ldo low noise < 40 v rms , "a" version stable with ceramic capacitors, v in : 2.1v to 20v, v out(min) = 1.21v, dropout voltage = 0.34v, i q = 1ma, i sd = <1 a, v out = 1.5, 1.8, 2.5, 3.3, dd, to220, sot-223, s8 packages lt1964 200ma, low noise micropower, negative ldo low noise < 30 v rms , stable with ceramic capacitors, v in : 0.9v to 20v, v out(min) = 1.21v, dropout voltage = 0.34v, i q = 30 a, i sd = 3 a, v out = adj., ?, thinsot package lt3020 100ma, vldo in msop low noise < 245 v rms , stable with 2.2 f ceramic capacitors, v in : 0.9v to 10v, v out(min) = 0.2 v, dropout voltage = 0.155v, i q = 140 a, i sd = <3 a, v out = adj., ms8, dfn packages lt3023 dual 100ma, low noise micropower, ldo dual low noise < 20 v rms , stable with 1 f ceramic capacitors, v in : 1.8v to 20v, v out(min) = 1.22 v, dropout voltage = 0.3v, i q = 40 a, i sd = <1 a, v out = adj., ms10, dfn packages lt3024 dual 100ma/500ma, low noise micropower, ldo dual low noise < 20 v rms , stable with 1 f/3.3 f ceramic capacitors, v in : 1.8v to 20v, v out(min) = 1.22 v, dro pout voltage = 0.3v, i q = 60 a, i sd = <1 a, v out = adj., t ssop16, dfn packages related parts

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